As the demand for more complex functions and higher performance in integrated circuits increases, it becomes necessary to reduce parasitic resistance elements of device structures as much as possible. One method which has been developed to reduce parasitic resistance values involves self-aligned silicide device structures. The conventional self-aligned silicide device structures include low resistance silicide layers formed over source/drain junctions regions and insulated polysilicon gate regions. Typically, a layer of refractory metal such as titanium is deposited and reacted in a nitrogen atmosphere. Titanium reacts with nitrogen to form a layer of titanium-nitride (TiN). Moreover, over exposed silicon areas, titanium reacts with and consumes silicon to form a layer of silicide (TiSix). The layer of TiN is removed selectively leaving silicided polysilicon gates and silicided source/drain junctions with reduced parasitic resistance elements.
Silicide has a much lower sheet resistance than doped polysilicon normally used to form the transistor gate regions. As a result, when the gate regions are silicided, the silicide shunts the higher resistance polysilicon. Accordingly, the silicided gate structures reduce the parasitic gate resistance and gate propagation delay due to this silicide electrical shunting effect. Moreover, the silicided source/drain junctions also have smaller parasitic resistance values and, as a result, provide larger extrinsic device transconductance values due to reduced series resistance. As the technologies scale below 0.5 micron features, the source/drain junctions become shallower to reduce the short channel effects, such as drain induced barrier lowering (DIBL) and punch-through leakage. This places a constraint on the amount of silicon consumption that can be tolerated due to the silicidation of the source/drain junction regions. This, in turn, places a constraint on the minimum allowable junction depth.
Prior art self-aligned silicide (SALICIDE) processes and silicided contact processes control the junction leakage by reducing the initial deposited refractory metal thickness. However, reducing the initial refractory metal thickness can result in excessive parasitic source/drain resistance values and transconductance degradation. Some alternative technologies have used an oxide layer between the initial titanium and silicon prior to the react process in order to improve the TiSi2/Si interface roughness. However, this approach has the drawback that it introduces oxygen in the silicide films. This is undesirable because it increases the resistivity of the silicide. Moreover, this method does not resolve the excessive silicon consumption problem when a sufficiently thick silicide layer is required for high-performance technologies.